FIG. 8 shows the construction of conventional full adder 8.
Full adder 8 is constructed of PMOS type transistors Q801-Q804, Q810, Q812, Q813, and Q815, NMOS type transistors Q805-Q808, Q809, Q811, Q814 and Q816, and inverters INV801-INV804. Of these, transistors Q809 and Q810, transistors Q811 and Q812, transistors Q813 and Q814, and transistors Q815 and Q816 are respectively transmission gates 800-806.
Full adder 8 performs full addition for input signals A and B and carry in signal C, that are input through input terminals A, B and C, respectively, shown in FIG. 8. The result is that addition results signal (sum signal) S.sub.out obtained is output through output terminal S.sub.out, and carry out signal C.sub.out is output through output terminal C.sub.out.
Full addition can be rapidly performed for input signals A and B and carry input C with full adder 8, shown as the prior art. However, the circuit that calculates sum signal S.sub.out and the circuit that calculates carry out signal C.sub.out are constructed very close together in full adder 8, so that a large number of transistor gates are connected to the signal line related to full addition, and the signals related to full addition will pass through a large number of transistors. Thus, there is the problem that the speed of operation of full adder 8 will be noticeably reduced by the effect of the I/O capacitance of the transistors that are not directly used for the operations because of the combinations of input signals A and B, and carry in signal C.
It is possible that the reduction in operating speed of full adder 8 caused by the transistor I/O capacitance can be improved to some extent by countermeasures, such as making the width of each transistor used for full adder 8 large and operating at high current. When measures such as these are taken, however, the area of each transistor in full adder 8 will become larger, and with this the area occupied on the semiconductor elements of full adder 8 will become larger, with the problem being that ultimately the increase in operating speed will not be what was desired. And simultaneously, there will be the problem of increased power consumption. Thus, the problem is that when conventional full adder 8 is used, it is difficult to realize high speed, high integration, and low power consumption simultaneously in the performance of DSP processing.
In addition, by combining the logic values of input signals A and B and carry in signal C, as will be discussed below with references to FIGS. 3 and 4, a difference in the effective capacitance which appears at the signal lines will occur, so the problem is that there will be significant variation in the operating speed of full adder 8. For example, the full addition time corresponding to combining the logic values of input signals A and B and carry in signal C, in a simulation example performed by the present inventors (evaluation with a power supply voltage of 2.7 V), varied between 1.36-3.57!,"D,|,. The problem is basically that the processing cycle of full adder 8 is kept to a worst value of 3.57.
In addition, in conventional full adders, the circuit for calculating the sum signal is generally more complex than the circuit that calculates the carry out signal. Thus the problem is that the processing time needed to calculated the sum signal is much longer than the processing time needed for calculating the carry out signal.
Recently there has been increased demand for processing all signals with a DSP mounted on digital cellular peripheral equipment which uses batteries as the power supply. Full adders for DSP used for this type of application require high-speed processing with low power supply voltage and low power consumption. Nearly all conventional general full adders, however, use circuit technology with 5 V power supply voltage, and in this case, processing will be severely reduced with power supply voltage of 3 V or less. Thus, the problem has been that DSPs that use conventional general full adders are not suitable for equipment that use batteries as the power supply.
My full adder was devised in consideration of the problems of the prior art discussed above. A first object is to provide a full adder that operates at low power supply voltage with minimal power consumption, even during high-speed processing, and which also occupies a small area on a semiconductor element.
In addition, a second object is to provide a full adder with which variation in the processing time corresponding to the combination of each of the input signals, and the processing time needed for calculating sum signals and for calculating carry in signals can be made smaller by reducing the number of transistor gates connected to the signal line related to processing.
In addition, it is a full adder that can be broadly applied to DSP in equipment that utilizes batteries as the power supply, for example, digital cellular communications peripherals, and in which high-speed operation and low power consumption is possible even with a conventional 5V power supply voltage.